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cmos-ccd signal processor for skew compensation description cxl1008m/p are cmos-ccd signal processors developed for the variable-speed video signal processor for home-use 8mm vcrs. features low power consumption 105mw (typ.) built-in peripheral circuit adjustment is necessary for one part. structure cmos-ccd functions 1/2h 359-bit, direct 20-bit ccd register clock driver timing oscillation circuit automatic bias circuit sync tip clamp circuit dummy vd insert circuit sample/hold circuit absolute maximum ratings (ta = 25?) supply voltage v dd 11 v v cl 6v operating temperature topr ?0 to +60 ? storage temperature tstg ?5 to +150 ? allowable power dissipaiton p d cxl1008m 500 mw cxl1008p 1000 mw recommended operating conditions supply voltage v dd 9v 5 % v cl 5v 5 % recommended clock conditions clock input amplitude v clk 0.15 to 1.0 (0.3 typ.) vp-p clock frequency f clk 10.738635 mhz ?1 e60248-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxl1008m/p cxl1008m 28 pin sop (plastic) cxl1008p 28 pin dip (plastic)
?2 cxl1008m/p block diagram 2 3 4 5 6 7 8 9 10 11 12 13 14 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 sig in1 mute in t7 t2 t1 t8 ext vd jog in v cl t6 clk in t5 t4 t3 v ss v ss v dd rec/pb auto sig in2 sig out sig delay ccd out feed out feed in skew in t9 t10 output control 50mv reference 50mv output circuit 1/2h d autobias circuit skew driver timing generator duty control f 1 f 2 pin configuration (top view) 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 v cl auto sig in2 sig in1 mute in t7 t6 clk in t5 t4 t3 t2 t1 v ss t8 ext vd jog in v ss sig out v dd sig delay rec/pb ccd out feed out feed in skew in t9 t10
?3 cxl1008m/p pin description pin no. 1 7 10 11 12 13 14 16 17 18 19 20 21 22 23 24 25 26 v ss clk in mute in sig in1 sig in2 auto v cl ext vd jog in v ss sig out v dd sig delay rec/pb ccd out feed out feed in skew in i i i i o i i o i i o o i i 0.3vp-p 5v when muting, normally 0v 1.1vp-p or less 2.2vp-p or less +5v 5v when vd is inserted jog mode 5v pb/rec mode 0v +9v 5v when pb 0v when rec gnd input the sine wave of 3fsc (10.738635mhz) the video signal mute is generated at high level. see the logic table of signal output selection state (table 1). signal input pin of ccd dl. input composite video signal. signal input pin of the through side. input composite video signal. the dc level of automatic bias is output. power supply 1 use this pin when vd is inserted to the video signal with the extrenal dummy vd signal input. jog/normal pb selection pin. see the logic table of signal output selection state (table 1). gnd final output power supply 2 after the output from pin 23 ccd out passes through lpf, input it to the same pin and insert clamp and vd. operate the clock at high when pb. stop the clock at low when rec. direct output from ccd dl feedback dc output smoothing capacitor connection pin of the bias commutation loop on the output circuit select direct dl and 1/2h dl signals when high and low, respectively. see the logic table of ccd dl mode selection (table 2). > 50k > 100k > 100k > 100k 10k > 100k > 100k 0.6 to 1.5k > 100k > 100k 0.6 to 1.5k 10k > 100k > 100k symbol i/o supply voltage description impedance ( ) note) t1 through t10 test pins must be connected as shown in the application circuit because of the ic internal circuit. notes on handling countermeasures for electrostatics are necessary because some pins have low electrostatic strength (particularly pin 26: skew in).
?4 cxl1008m/p items power current clock input level signal input pin voltage signal output pin voltage ccd signal output voltage difference signal insert gain ccd output signal gain difference frequency characteristics frequency characteristics difference differential gain i dd i cl clk vdi1 vdi2 vdi3 vdo1 vdo2 ? dab ig ccd ig in2 ig dl ? gab f ccd f in2 f dl ? fab dg ccd dg in2 dg dl pb, jog direct ? ? 1/2h direct ? ? 1/2h 3.58mhz/100khz 10mhz/100khz 10mhz/100khz direct ? ? 1/2h at 3.58mhz 1.1vp-p input 2.2vp-p input 2.2vp-p input c c c b a c b c c b a c c b a c c b a a a a a a a a a b b b b b b b b b b b a a e e e e e e a f f a b ? ? c b ? ? d b ? ? d b ? ? c g g g a a b b a a b b a a b b a a a a a b b b b c c c l l l l l l l l l l l l l l l l h l h l h h h h h h h h h h h h h ? ? l h ? ? l h ? ? l 0.15 4.0 4.0 4.0 1.7 1.5 ?5 ?.0 ?.2 ?.2 ?.3 ? ?.5 ?.5 ?.2 0 0 0 7 8 0.3 5.0 4.2 4.2 2.0 2.0 0 0 ?.8 ?.8 0 ? 0 0 0 3 2 2 12 10 1.0 6.0 4.4 4.4 2.4 2.5 55 3.0 0 0 1.3 0 0.2 10 4 4 ma ma v v v v v v mv db db db % db db db db % % % 1 1 2 2 2 3 3 4 5 5 5 6 7 8 8 9 10 10 10 symbol test conditions switch conditions control pin conditions * 1 , * 2 min. typ. max. unit note 1 2 3 4 5 p1 p2 p3 p4 p5 electrical characteristics (see the electrical characteristics test circuit) (ta = 25?, v dd = 9.0v, v cl = 5.0v, f clk = 10.7mhz, v clk = 0.3vp-p sine wave)
?5 cxl1008m/p items differential phase allowable input amplitude s/n rate vd insert depth logical input dp ccd dp in2 dp dl v in1?c v in2?c s/n ccd s/n in2 s/n dl v vd v in h v in l 1.1vp-p input 2.2vp-p input 2.2vp-p input 2vp-p video signal from sync tip c b a c a/b c b a a b b b b b b a g g g g g a ? ? e f ? ? e f ? ? e g a b b a b b b c c c d d d a l l l l l l l l l l h l h h h h 0 0 0 50 50 50 0 4.0 3 3 3 55 65 65 50 5 5 5 1.1 2.2 100 1.0 deg deg deg vp-p vp-p db db db mv v v 10 10 10 11 11 11 12 symbol test conditions switch conditions control pin conditions * 1 , * 2 min. typ. max. unit note 1 2 3 4 5 p1 p2 p3 p4 p5 * 1 control pins correspond to p1 through p5 of the electrical characteristics test circuit. * 2 symbols "h" and "l" in control pin conditions represent "v in h " and "v in l " of logical input.
?6 cxl1008m/p p2 p3 p5 2 3 4 5 6 7 8 9 10 1 a sw5 b c d 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0.1 v3 22 10k 10 220k p4 5v 2sa1175 9v 2sa1175 2k a2 9v v2 2k 5v 390k sw4 a b 0.1 1 lpf bpf note 1) note 2) 1 0.1 1 1 oscilloscope spectrum analyzer vector scope noise meter 100k 5v clk p1 5v 10 a1 sw1 a b c v1 sw2 a b 20k 1m v bias 0.1 sw3 a b c d e f g 100khz 1.1vp-p sine wave 100khz 300mvp-p sine wave 3.58mhz 300mvp-p sine wave 10mhz 300mvp-p sine wave ground 100khz 2.2vp-p sine wave 5-stair case wave 0 5.8 10.7 frequency [mhz] ?0 ? 0 note 1) lpf frequency response (delay time to 140ns) 0 4.1m 10.7m frequency [hz] ?0 ? 0 50 [db] [db] note 2) bpf frequency response 200 electrical characteristics test circuit
?7 cxl1008m/p notes) 1) current value when the clock is in operation in the pb or jog mode. in the rec mode, the clock is stopped (pin 22 is at low) to save power. 2) with the signal input pin voltage value, the video signal sync tip is clamped. 3) vdo1 is a ccd out output voltage when the sig in1 input voltage is vdi1. vdo2 is a sig out output voltage when the sig in2 input voltage is vdi2. vdo1 and vdo2 represent outputs for the sync tip clamp level when a white level signal is input as shown in the diagram. 1.0vp-p 100% 40% vdi input signal vdo output signal 4) ? dab denotes an output voltage difference of ccd out when the direct dl and 1/2h dl are switched. 5) ig ccd is a ccd out gain when a 1.1vp-p 100khz sine wave is input to sig in1. ig ccd = 20 log output amplitude (vp-p) 1.1vp-p it is measured by giving a vdi1 + 0.6 bias with v bias . igin2 and ig dl are sig out gains when 2.2vp-p 100khz sine wave is input to each of sig in2 and sig delay pins. igin2 = 20 log output amplitude (vp-p) 2.2vp-p it is measured by giving a vdi2 + 1.1v bias with v bias .
?8 cxl1008m/p 6) ? gab is a gain difference between the direct dl and 1/2h dl. 7) it represents a loss at 3.58mhz compared with 100khz. it is measured by raising the sig in1 input pin by 0.6v higher than the sync tip clamp level (vdi1) with v bias . v bias = vdi1 + 0.6v 3.85mhz 300mvp-p sine wave 100khz 300mvp-p sine wave sig in1 dc f ccd = 20 log v3.58mhz output v100khz output 8) it represents a loss at 10mhz compared with 100khz. it is measured by raising the sig in2 or sig delay input pin by 1.1v higher than the sync tip clamp level (vdi2 or vdi3) with v bias . 9) ? fab is a frequency response difference between the direct dl and 1/2h dl. 10) chroma 40 ire 140 ire 40 ire 1h 63.5s 1.1vp-p at dg ccd 2.2vp-p at dg in2 or dg dl dg is measured with a vectorscope in each mode of the 5-stage waves. 11) measure s/n of the bpf 100khz to 4.2mhz in the subcarrier trap mode with a video noise meter. 12) 2vp-p v vd sig delay input waveform ext vd input sig out output waveform set a voltage value at v vd when inserting ext vd to the 2vp-p signal output waveform sync tip of sig out.
?9 cxl1008m/p 3fsc (10.738635mhz) sine wave 0.15 to 1.0vp-p clock function outline output signal selection 50mv ref sig out sig in2 (pb) sig delay (jog) the video output signal is selected by selecting the output switch for three signals: pin 10 (mute in), pin 17 (jog in) and pin 16 (ext vd). table 1. logic table of signal output selection state input control signal state video signal output selection state jog in 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 o o o o o o o o o mute in ext vd pb jog vd insert mute note 1) figures "0" and "1" of the input control signal state are equivalent to "low" and "high" of logic. note 2) items marked with the symbol "o" in the video signal output selection state are selected. note 3) pb = jog in ?mute in jog = jog in ?mute in ?ext vd vd insert = jog in ?ext vd mute = mute in
?10 cxl1008m/p ccd selection ccd out sig in1 skew in 1/2h (359bit) d (20bit) table 2. logic table of ccd dl mode selection control signal skew in 0 1 d o 1/2h o ccd dl mode application circuit 3fsc 0.3vp-p sine wave ext vd jog in 2 3 4 5 6 7 8 9 10 1 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 0.01f 22 10k 10 rec/pb 9v 1k 560 220k 100k mute in 5v 10 2m 0.047 2m 0.047 510 signal input 510 47 1000p transistor to be used pnp: 2sa1175 signal output 1.5k 1.8k 120 10h 220p 270p 0.022 220 8.2k 390 390 4.7k 2.2k 10k 220k 18k 10 2k 10 1000p 47 1m skew in frequency characteristics (ta = 25?) 10k 100k 1m f ?frequency [hz] gain [db] ? ? 0 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?11 cxl1008m/p 5.00 4.75 v cl ?supply voltage [v] supply voltage (v cl ) vs. insert gain (ig ccd ) ig ccd ?insert gain [db] ? ? 0 1 2 ? 5.25 5.00 4.75 v cl ?supply voltage [v] supply voltage (v cl ) vs. frequency characteristics (f ccd ) f ccd ?frequency characteristics [db] ? ? ? 0 1 ? 5.25 5.00 4.75 v cl ?supply voltage [v] supply voltage (v cl ) vs. differential gain (dg ccd ) dg ccd ?differential gain [%] 1 2 3 4 5 0 5.25 5.00 4.75 v cl ?supply voltage [v] supply voltage (v cl ) vs. output pin voltage (v do 1) v do 1 ?output pin voltage [v] 2.0 2.5 1.5 5.25 9.0 8.5 v dd ?supply voltage [v] supply voltage (v dd ) vs. insert gain (ig ccd ) ig ccd ?insert gain [db] ? ? 0 1 2 ? 9.5 9.0 8.5 v dd ?supply voltage [v] supply voltage (v dd ) vs. frequency characteristics (f ccd ) f ccd ?frequency characteristics [db] ? ? ? 0 1 ? 9.5
?12 cxl1008m/p 9.0 8.5 v dd ?supply voltage [v] supply voltage (v dd ) vs. differential gain (dg ccd ) dg ccd ?differential gain [%] 1 2 3 4 5 0 9.5 9.0 8.5 v dd ?supply voltage [v] supply voltage (v dd ) vs. output pin voltage (v do 1) v do 1 ?output pin voltage [v] 2.0 2.5 1.5 9.5 20 0 ta ?ambient temperature [?] ambient temperature (ta) vs. insert gain (ig ccd ) ig ccd ?insert gain [db] ? ? 0 1 2 ? 60 40 20 0 ta ?ambient temperature [?] ambient temperature (ta) vs. differential gain (dg ccd ) dg ccd ?differential gain [%] 1 2 3 4 5 0 60 40 20 0 ta ?ambient temperature [?] ambient temperature (ta) vs. frequency characteristics (f ccd ) f ccd ?frequency characteristics [db] ? ? ? 0 1 ? 60 40 20 0 ta ?ambient temperature [?] ambient temperature (ta) vs. output pin voltage (v do 1) v do 1 ?output pin voltage [v] 2.0 2.5 1.5 60 40
?13 cxl1008m/p package outline unit: mm cxl1008m 28pin sop (plastic) 18.8 ?0.1 + 0.4 0.45 0.1 1.27 10.3 0.4 7.6 ?0.1 + 0.3 0.5 0.2 0.15 ?0.05 + 0.1 0.1 ?0.05 + 0.2 2.3 ?0.15 + 0.4 m 0.24 sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy sop-28p-l02 sop028-p-0375 0.6g 9.3 114 28 15 0.15 cxl1008p sony code eiaj code jedec code package structure package material lead treatment lead material package mass epoxy resin solder plating copper alloy dip-28p-03 dip028-p-0600 4.2g 28pin dip (plastic) 37.8 ?0.1 + 0.4 28 15 114 2.54 0.5 0.1 1.2 0.15 3.0 min 0.5 min 4.6 ?0.1 + 0.4 15.24 13.0 ?0.1 + 0.3 0.25 ?0.05 + 0.1 0?to 15 1.all mat surface type. two kinds of package surface: 2.center part is mirror surface.

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